1. Field of the Invention
The present invention relates to a semiconductor memory device and a control method thereof, and more particularly to a semiconductor memory device that improves the equalizing operation of bit lines and a control method thereof.
2. Description of Related Art
In a semiconductor memory device such as a dynamic random access memory (hereinafter referred to as “DRAM”), there is a shared sense amplifier system that shares one sense amplifier group by two memory blocks. In this case, in order to separate a bit line within an unselected memory block from a sense amplifier, a bit line separation gate (BT) is disposed.
FIG. 10 is a diagram showing a part of a shared sense amplifier system. A sense amplifier S/A is connected between a bit line BLZ and a complementary bit line BLX, and shared by memory blocks BLK1 and BLK2 adjacent to each other. Separation gates BTL and BTR are connected between the respectively corresponding memory blocks BLK1, BLK2 and the sense amplifier S/A, and perform conduction and non-conduction in response to the corresponding separation gate control signals sbltlx and sbltrx. The bit lines are equalized by an equalizer circuit 150 disposed at the sense amplifier.
In this example, an alternate sense amplifier S/As may be replaced by the sense amplifier S/A. In the above-mentioned sense amplifier S/A, an inner step-down voltage Vcc is applied to a sense amplifier active line PSA, and a ground voltage Vss is applied to a sense amplifier active line NSA, to thereby bring the sense amplifier S/A into an active state. On the other hand, in the alternate sense amplifier S/As, when an alternate sense amplifier active signal LEX of a low level is inputted to a transistor Tr9, and an alternate sense amplifier active signal LEZ of a high level is inputted to a transistor Tr10, Vcc and Vss are then applied to the alternate sense amplifier S/As, to thereby bring the alternate sense amplifier S/A into an active state.
FIG. 11 is a timing chart showing self refresh operation. The self refresh operation is conducted in response to a “high” level (active) of a self-refresh enable signal SREFE. In a period of time when the block BLK1 is self-refreshed, the control signal sbltlx is kept in the “high” level, the separation gate BTL is rendered conductive, and the bit lines BLLZ and BLLX within the block BLK1 continue to be connected to the bit lines BLZ and BLX that are connected with the sense amplifier S/A. During the period of time, word lines sw10, sw11, . . . are sequentially activated in response to the “low” level transition of /RAS that is an internal RAS signal, and the bit lines BLLZ and BLLX are restored. Simultaneously, the word lines sw10, sw11, . . . are inactivated in response to the “high” level transition of /RAS, and the bit lines BLLZ and BLLX are equalized.
Also, the separation gate BTR on the unselected block BLK 2 side is rendered conductive by putting the control signal sbltrx into the “high” level every period where /RAS is “high” level, that is, every period where the bit line of the BLK1 is equalized. As a result, the bit lines BLRZ and BLRX of the unselected block BLK2 are connected to the bit lines BLZ and BLX and equalized. Meanwhile, when the block BLK2 is self-refreshed, the same equalization control is conducted on the block BLK1. Subsequently, the same operation is conducted on the respective blocks, to thereby complete self refresh with respect to all of the memory cells.
On the other hand, as disclosed in JP 9-161477A and JP 10-222977A, in the control shown in FIG. 12, the control signal of the separation gate on the unselected block side is always kept in the “low” level in a refresh period of the memory cell on the selected block side. For that reason, the sense amplifier S/A and the bit line on the unselected block side are not connected to each other even during the equalizing period of the selected block. Unlike with the case shown in FIG. 11 where the unselected block is connected, the separation gate that is connected to the unselected block does not conduct switching operation every time the selected block is equalized, thereby reducing charge and discharge current.
In a semiconductor memory device disclosed by JP 8-153391A and JP 9-45879A, a bit line equalizer circuit is disposed in each of memory blocks separated from the sense amplifier with the bit line separation gate. Accordingly, the equalizing operation is conducted by means of the bit line equalizer circuit disposed in the unselected memory block even in a period where a bit line between the unselected memory block and the sense amplifier is rendered nonconductive. As a result, the potential displacement caused by the floating state of the bit line potential can be prevented.
Also, in FIG. 10, both of a bit line equalization control signal BRS, and an equalization control signal BRSS of sense amplifier active lines PSA/NSA are controlled between a step-up voltage Vpp and the ground voltage Vss. The driving performance of an equalization transistor is enhanced by driving with the step-up voltage Vpp that has been stepped up from an external supply voltage Vdd, thereby reduce an equalization period of time.
Also, in the recent semiconductor memory device, in order to increase the speed of the restoring operation or improve the sensitivity to accumulated charges by using the sense amplifier, a bit line length may be shortened. With this structure, the wiring capacity of the bit line is reduced, and a reduction in the current consumption at the time of restoring and a reduction in the equalization period of time are tried.